Projects

Conference Papers and Presentations:

o       J. Gambino, S.Adderly, J. Knickerbocker, A Review of Thru-Silicon-Via Technology ManufacturingChallenges for Vertical Chip Integration, Microelectronic Engineering, Fall 2014

o       J. Gambino, N. Bowe, D. Bronson, S. Adderly, Imaging of Through Silicon Vias using X-Ray Tomography, International Symposium on the Physical and Failure Analysis of Integrated Circuits,Singapore, June 2014

o       M. Moon, S. Adderly, J. Gambino, B. Cucci, J. Hanrahan, The Effect of Backside Roughness on SOI Interconnects, Advanced Semiconductor Manufacturing Conference, Saratoga Springs, NY, May 2014

o       S.Adderly, M. Moon, M. Lifson, N. Bowe, J. Gambino and T. Sullivan, The Effect of Etch Residualson Via Reliability, IEEE Conference on Reliability Science for Advanced Materials and Devices,Golden, CO, February 2013

o       S. Adderly, T. Speranza, N.Zhou, G.Endicott, L.Chan, A.Shelden and S. Williams, A Standardized, Approach to Foundry Program Management, IEEE Burlington Technology Conference, Burlington,VT, June 2012

o       S. Adderly, J. Gambino, T. Sullivan, M. Moon, T. Speranza, N. Bowe, and D. Thomas, A Process to Reduce the Occurrence of Metal Extrusions in Al Interconnects, Advanced Semiconductor Manufacturing Conference, Saratoga Springs, NY, May 2012

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